Non-volatile semiconductor memory device

ABSTRACT

A non-volatile semiconductor memory device is proposed whereby voltage can be more flexibly set in accumulating electric charges into a selected memory cell transistor in comparison with a conventional device. In a non-volatile semiconductor memory device ( 1 ), when a selected memory cell transistor ( 115 ) is caused to accumulate electric charges, high voltage as writing prevention voltage is applied from a PMOS transistor ( 9 b) while low voltage as writing voltage is applied from an NMOS transistor ( 15 a). Thus, a role of applying voltage to either the selected memory cell transistor ( 115 ) or a non-selected memory cell transistor ( 116 ) is shared by the PMOS transistor ( 9 b) and the NMOS transistor ( 15 a). Therefore, the gate voltage and the source voltage of the PMOS transistor ( 9 b) and those of the NMOS transistor ( 15 a) can be separately adjusted, and gate-to-substrate voltage thereof can be finally set to be, for instance, 4[V] or etc.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is the U.S. National Phase of International PatentApplication Serial No. PCT/JP2012/073849 filed Sep. 18, 2012, whichclaims the benefit of Japanese Patent Application Serial No.2011-205934, filed Sep. 21, 2011, both of which are incorporated hereinby reference in their entireties.

TECHNICAL FIELD

The present invention relates to a non-volatile semiconductor memorydevice.

BACKGROUND ART

As an exemplary non-volatile semiconductor memory device, a type ofnon-volatile semiconductor memory device has been conventionally knownthat accumulates electric charges into a charge accumulation layer of amemory cell transistor by means of, for instance, a quantum tunnelingeffect in order to execute data writing (e.g., see PTL 1). Actually, asshown in FIG. 6, a non-volatile semiconductor memory device 100 of thistype has a structure that higher order bit lines 101a and 101b and wordlines 102a to 102h are disposed in an intersecting manner and aplurality of memory cell transistors 103 are disposed in a row andcolumn matrix with respect to the higher order bit lines 101a and 101band the word lines 102a to 102h.

The higher order bit line 101a is provided with a plurality of firstsemiconductor switches 104a and 104c, while a single lower order bitline 105a, 105c is connected to each first semiconductor switch 104a,104c. Further, in this exemplary embodiment, the other higher order bitline 101b is also similarly provided with a plurality of firstsemiconductor switches 104b and 104d, while a single lower order bitline 105b, 105d is connected to each first semiconductor switch 104b,104d. In such non-volatile semiconductor memory device 100, each lowerorder bit line 105a, 105b, 105c, 105d forms a memory block 106a, 106b,106c, 106d, while each memory block 106a, 106b, 106c, 106d has theplural memory cell transistors 103.

The first semiconductor switches 104a, 104b, 104c and 104d are hereinformed by N-MOS (Metal-Oxide-Semiconductor) transistors. Further, thefirst semiconductor switch 104a of the memory block 106a, for instance,is connected at the source thereof to the higher order bit line 101awhile being connected at the drain thereof to the lower order bit line105a, and is also connected at the gate thereof to a first selected gateline 108a shared with another memory block 106b aligned with the memoryblock 106a along a row direction. Thus, by this configuration, apredetermined gate voltage can be equally applied from the shared,single first selected gate line 108a to the two first semiconductorswitches 104a and 104b that are mounted on the memory blocks 106a and106b disposed in the upper part of FIG. 6.

On the other hand, similarly also in the two memory blocks 106c and 106daligned along the row direction in the lower part of FIG. 6, a singlefirst selected gate line 108b is connected to the two firstsemiconductor switches 104c and 104d, and a predetermined gate voltageis can be configured to be equally applied to the two firstsemiconductor switches 104c and 104d from the shared, first selectedgate line 108b.

In addition to this, a higher order source line 110a is provided with aplurality of second semiconductor switches 111a and 111b, while a singlelower order source line 112a, 112b is connected to each secondsemiconductor switch 111a, 111b. Further, the other higher order sourceline 110b is also similarly provided with a plurality of secondsemiconductor switches 111c and 111d, while a single lower order line112c, 112d is connected to each second semiconductor switch 111c, 111d.

Further, the second semiconductor switches 111a, 111b, 111c and 111d areformed by NMOS transistors that the polarity thereof is the same as thatof the first semiconductor switches 104a, 104b, 104c and 104d.

Herein, the second semiconductor switch 111a of the memory block 106a,for instance, is connected at the source thereof to the higher ordersource line 110a while being connected at the drain thereof to the lowerorder source line 112a, and is also connected at the gate thereof to asecond selected gate line 113a shared with another memory block 106baligned along the row direction in the upper part. Thus, a predeterminedgate voltage can be configured to be equally applied from the shared,single second selected gate line 113a to the two second semiconductorswitches 111a and 111b that are mounted on the different memory blocks106a and 106b disposed in the upper part.

On the other hand, similarly also in the two memory blocks 106c and 106daligned along the row direction in the lower part, a single secondselected gate line 113b is connected to the two second semiconductorswitches 111c and 111d, and a predetermined gate voltage can beconfigured to be equally applied to the two second semiconductorswitches 111c and 111d from the shared, second selected gate line 113b.

Further, each memory cell transistor 103 on the memory block 106a, forinstance, is connected at one terminal thereof to the lower order bitline 105a while being connected at the other terminal thereof to thelower order source line 112a, and thus, the memory cell transistors 103are disposed in parallel to each other between the lower order bit line105a and the lower order source line 112a. The word lines 102a, 102b,102c and 102d, shared by the memory block 106a and another memory block106b aligned along the row direction, are connected to control gates ofthe memory cell transistors 103 of the memory block 106a. Due to this, apredetermined gate voltage can be configured to be equally applied, forinstance, from the shared, single word line 102a to one of the memorycell transistors 103 of the memory block 106a in the upper part and oneof the memory cell transistors 103 of another memory block 106b alignedwith the memory block 106a along the row direction in the upper part.

Incidentally, all the memory cell transistors 103 have the samestructure that a channel region is disposed between one terminal and theother terminal, which are formed at a predetermined interval on asemiconductor substrate, and a charge accumulation layer, an interlayerinsulation layer and a control gate are sequentially laminated through atunnel insulation layer on the channel region of the semiconductorsubstrate. Such memory cell transistors 103 are of an N-channel type,and are capable of executing either data writing by injecting electriccharges into the charge accumulation layer or data erasing by extractingthe electric charges accumulated into the charge accumulation layer bymeans of voltage to be applied to the control gate and the regionbetween the one terminal and the other terminal.

The non-volatile semiconductor memory device 100 thus structured can beconfigured to write data in a predetermined one of the memory celltransistors 103, read data from a predetermined one of the memory celltransistors 103 and erase data written in the memory cell transistors103 by regulating voltages to be respectively applied to the higherorder bit lines 101a and 101b, the higher order source lines 110a and110b and the word lines 102a to 102h and by controlling on/off states ofthe first semiconductor switches 104a to 104d and the secondsemiconductor switches 111a to 111d.

In FIG. 6, the memory cell transistor 103 in the first row of the memoryblock 106a is set as a selected memory cell transistor 115 in which datais written, whereas all the remaining memory cell transistors 103 areset as non-selected memory cell transistors 116 in which data is notwritten.

It should be herein noted that for the sake of explanatory convenience,the memory block 106a on which the selected memory cell transistor 115is disposed will be referred to as a selected block 117, whereas thememory blocks 106b, 106c and 106d on which only the non-selected memorycell transistors 116 are disposed will be referred to as non-selectedblocks 118.

Actually in the non-volatile semiconductor memory device 100, forinstance, when data is written in only the selected memory celltransistor 115 in the first row of the selected block 117, a highvoltage of 12[V] is applied to a word line 120 (hereinafter referred toas a selected word line) that is the one connected to the selectedmemory cell transistor 115 among the plural word lines 102a to 102h,whereas a low voltage of 4[V] is applied to the word lines 121(hereinafter referred to as non-selected word lines) that are the otherremaining ones among the plural word lines 102a to 102h.

Further, at this time, in the non-volatile semiconductor memory device100, a low voltage of 0[V] as a writing voltage can be applied to ahigher order bit line 122 (herein referred to as a selected bit line)that is the one to which the selected memory cell transistor 115 isconnected, whereas a high voltage of 8[V] as a writing preventionvoltage can be applied to a higher order bit line 123 (herein referredto as a non-selected bit line) that is the one to which only thenon-selected memory cell transistors 116 are connected. Moreover, in thenon-volatile semiconductor memory device 100, a gate voltage of 10[V],which is higher than the voltage of the non-selected bit line 123, canbe applied to the first semiconductor switches 104a and 104b from thefirst selected gate line 108a connected to the selected block 117,whereas a gate voltage of 0[V] can be applied to the secondsemiconductor switches 111a and 111b from the second selected gate line113a.

Accordingly, in the non-volatile semiconductor memory device 100, thefirst semiconductor switch 104b on the non-selected bit line 123 isswitched on by means of the writing prevention voltage from thenon-selected bit line 123 and the gate voltage from the first selectedgate line 108a, and a writing prevention voltage of 8[V] can be appliedto the non-selected memory cell transistor 116 on the non-selected bitline 123 that intersects with the selected word line 120. At this time,the second semiconductor switches 111a, 111b, 111c and 111d are switchedoff by applying a voltage of 0[V] thereto from the higher order sourcelines 110a and 110b and by applying a voltage of 0[V] thereto from thesecond selected gate lines 113a and 113b, and the lower order sourcelines 112a, 112b, 112c and 112d can be turned into a floating state.

Thus, in the non-selected memory cell transistor 116 at which theselected word line 120 and the non-selected bit line 123 intersect witheach other, a voltage difference is reduced between the control gate andthe semiconductor substrate, and as a result, electric charges cannot beinjected into the charge accumulation layer without occurrence of aquantum tunneling effect.

Further, at this time, the first semiconductor switch 104a on theselected bit line 122 is switched on by means of the writing voltagefrom the selected bit line 122 and the gate voltage from the firstselected gate line 108a, and a writing voltage of 0[V] can be applied tothe selected memory cell transistor 115 on the selected bit line 122that intersects with the selected word line 120. Accordingly, in theselected memory cell transistor 115 at which the selected word line 120and the selected bit line 122 intersect with each other, a voltagedifference is increased between the control gate and the semiconductorsubstrate by means of the writing gate voltage applied from the selectedword line 120. As a result, a quantum tunneling effect occurs andelectric charges can be injected into only the charge accumulation layerof the relevant selected memory cell transistor 115. Consequently, inthe non-volatile semiconductor memory device 100, only the selectedmemory cell transistor 115 can be set to be in a data written statewhile electric charges are accumulated into the charge accumulationlayer thereof.

CITATION LIST Patent Literature

-   PTL1: Japanese Patent Laid-open No. H10-144807

SUMMARY OF INVENTION Technical Problem

However, the non-volatile semiconductor memory device 100 thusstructured has had a drawback that in applying writing preventionvoltage from the non-selected bit line 123 to the non-selected memorycell transistor 116 on the selected word line 120, it is required toapply a gate voltage of roughly 10[V], which is higher than a writingprevention voltage of 8[V] applied from the non-selected bit line 123,in order to switch on the first semiconductor switch 104b due to thefirst semiconductor switch 104 formed by an NMOS transistor, andtherefore, voltage is inevitably increased by that much.

Further, the first selected gate line 108a is connected not only to thefirst semiconductor switch 104b on the non-selected bit line 123 butalso to the first semiconductor switch 104a on the selected bit line 122that applies writing voltage to the selected memory cell transistor 115.Therefore, a high gate voltage of 10[V], which is set to be relativelyhigh for switching on the first semiconductor switch 104b on thenon-selected bit line 123, can be also applied without change to thefirst semiconductor switch 104a on the selected bit line 122.

Thus, gate voltages having the same voltage value are equally applied tothe first semiconductor switch 104a switched into an on-state on thenon-selected bit line 123 and the first semiconductor switch 104bswitched into an on-state on the selected bit line 122. Hence, there hasbeen a drawback that it is difficult to execute a flexible setting, suchas separately regulating respective gate voltages in order to reduce thevoltage values of the respective gate voltages, in applying electriccharges to a selected memory transistor.

Hence, the present invention has been made in consideration of theabove, and is intended to propose a non-volatile semiconductor memorydevice whereby voltage in accumulating electric charges into a selectedmemory cell transistor can be further reduced and can be more flexiblyset in comparison with a conventional device.

Solution to Problem

To solve the aforementioned problem, claim 1 of the present inventionrelates to a non-volatile semiconductor memory device that includes: aplurality of memory cell column wirings to which a charge accumulatingvoltage or a charge accumulating prevention voltage is applied; and aplurality of memory cell transistors having an N-channel type structureand disposed in a row and column matrix with respect to the plurality ofmemory cell column wirings and a plurality of word lines, and thatcauses a selected memory cell transistor in the plurality of memory celltransistors to accumulate electric charges based on a voltage differencebetween the charge accumulating voltage and a voltage to be applied tothe word lines. The non-volatile semiconductor memory device comprises:a plurality of first semiconductor switches formed by PMOS transistors,the first semiconductor switches being provided for the respectivememory cell column wirings; and a plurality of second semiconductorswitches formed by NMOS transistors, the second semiconductor switchesbeing provided for the respective memory cell column wirings, wherein,in a non-selected memory cell column wiring in which only non-selectedmemory cell transistors except for the selected memory transistor aredisposed, the first semiconductor switches are configured to be switchedon by means of a first gate voltage and to apply the charge accumulatingprevention voltage to the non-selected memory cell transistors whereas,in a selected memory cell column wiring in which the selected memorycell transistor is disposed, the second semiconductor switches areconfigured to be switched on by means of a second gate voltage and toapply the charge accumulating voltage to the selected memory celltransistor.

Advantageous Effects of Invention

According to the present invention, when the selected memory celltransistor is caused to accumulate electric charges, aside from thefirst semiconductor switches applying the charge accumulating preventionvoltage to the non-selected memory cell transistors, the secondsemiconductor switches are provided that are formed with a polarityopposite to that of the first semiconductor switches, and the secondsemiconductor switches are configured to be switched on by means of thesecond gate voltage and to apply the charge accumulating voltage to theselected memory cell transistor. Accordingly, it is possible toseparately set the first gate voltage switching on the firstsemiconductor switches and the second gate voltage switching on thesecond semiconductor switches. Thus, it is possible to more flexibly setvoltage in accumulating electric charges into the selected memory celltransistor in comparison with a conventional device.

Further, according to the present invention, for instance, the firstgate voltage for switching on the first semiconductor switches and thesecond gate voltage for switching on the second semiconductor switchescan be also separately reduced to have low voltage values capable ofswitching on the first semiconductor switches and the secondsemiconductor switches without being constrained by each other. It isthereby possible to reduce a voltage difference between a substrate anda gate in each first semiconductor switch of a switched-on state andthat in each second semiconductor switch of a switched-on state Thus, itis also possible to further relax electric fields to be applied to therespective gate insulating films in comparison with a conventionaldevice.

Yet further, according to the present invention, the PMOS transistorsare applied as the first semiconductor switches, while the NMOStransistors are applied as the second semiconductor switches. Therefore,the first gate voltage for switching on the PMOS transistors can besuppressed lower than the charge accumulating prevention voltage havinga relatively high voltage value. Thus, voltage in accumulating electriccharges into the selected memory cell transistor can be further reducedby that much in comparison with a conventional device.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram showing a circuit configuration of anon-volatile semiconductor device according to a first embodiment.

FIG. 2 is a circuit diagram showing voltage values in the respectivepositions in a data writing action of the non-volatile semiconductormemory device according to the first embodiment.

FIG. 3 is a circuit diagram showing voltage values in the respectivepositions in a data reading action of the non-volatile semiconductormemory device.

FIG. 4 is a circuit diagram showing voltage values in the respectivepositions in a data erasing action of the non-volatile semiconductormemory device.

FIG. 5 is a circuit diagram showing voltage values in the respectivepositions in a writing action according to a first exemplarymodification.

FIG. 6 is a circuit diagram showing a circuit configuration of aconventional non-volatile semiconductor memory device.

REFERENCE SIGNS LIST

1, 25 Non-volatile semiconductor memory device

-   2a, 2b Memory cell column wiring-   9a, 9b, 9c, 9d PMOS transistor (first semiconductor switch)-   15a, 15b, 15c, 15d NMOS transistor (second semiconductor switch)-   18a Selected memory cell column wiring-   18b Non-selected memory cell column wiring-   102a to 102h Word line-   103 Memory cell transistor-   115 Selected memory cell transistor-   116 Non-selected memory cell transistor

DESCRIPTION OF THE EMBODIMENTS

Exemplary embodiments of the present invention will be hereinafterexplained in detail with reference to the drawings.

(1) First Embodiment

(1-1) Entire Structure of Non-Volatile Semiconductor Memory Device

In FIG. 1 shown with the same reference signs assigned to componentscorresponding to those in FIG. 6, a non-volatile semiconductor memorydevice according to the present invention is indicated by a referencesign 1, and a plurality of memory cell column wirings 2a and 2b and aplurality of word lines 102a to 102h are provided, while plurality ofmemory cell transistors 103 are disposed in a row and column matrix withrespect to the memory cell column wirings 2a and 2b and the word lines102a to 102h. The two memory cell column wirings 2a and 2b herein havethe same structure. Therefore, for the sake of explanatory convenience,one of the memory cell wirings, i.e., the memory cell wiring 2a isfocused while explanation of the other memory cell wiring 2b will beomitted.

Actually, the memory cell column wiring 2a is formed by a bit line 4aand a source line 5a, and has a structure that the plural memory celltransistors 103 are disposed in parallel to each other between the bitline 4a and the source line 5a. In the exemplary embodiment, the bitline 4a is formed by a higher order bit line 7a and two lower order bitlines 8a and 8c. The higher order bit line 7a is provided with aplurality of PMOS transistors 9a and 9c, while the single lower orderbit line 8a, 8c is connected to each PMOS transistor 9a, 9c.

It should be noted that in FIG. 1, similarly in another bit line 4b, ahigher order bit line 7b is provided with a plurality of PMOStransistors 9b and 9d, while a single lower order bit line 8b, 8d isconnected to each PMOS transistor 9b, 9d as a first semiconductorswitch. Thus, in the non-volatile semiconductor memory device 1, the twohigher order bit lines 7a and 7b are provided with totally four lowerorder bit lines 8a, 8b, 8c and 8d, while a memory block 10a, 10b, 10c,10d is formed for each lower order bit line 8a, 8b, 8c, 8d. The fourmemory blocks 10a, 10b, 10c and 10d, formed for the respective lowerorder bit lines 8a, 8b, 8c and 8d, herein have the same structure.Therefore, for the sake of explanatory convenience, one of the memoryblocks, i.e., the memory block 10a is focused and explained, whileexplanation of the other memory blocks lob, 10c and 10d will be omitted.

Unlike the conventional non-volatile semiconductor memory device 100,the non-volatile semiconductor memory device 1 according to the presentinvention is characterized in that, not NMOS transistors, but the PMOStransistors 9a, 9b, 9c and 9d are provided as the first semiconductorswitches between the higher order bit line 7a and 7b and the lower orderbit lines 8a, 8b, 8c and 8d. For example, the PMOS transistor 9a on thememory block 10a is connected at the source thereof to the higher orderbit line 7a while being connected at the drain thereof to the lowerorder bit line 8a, and is also connected at the gate thereof to a firstselected gate line 108a extended in the row direction. The firstselected gate line 108a is connected to the PMOS transistors 9a and 9bthat are respectively mounted on the memory blocks 10a and 10b alignedalong the row direction in the upper part.

Thus, a predetermined gate voltage can be configured to be equallyapplied from the shared, single first selected gate line 108a to the twoPMOS transistors 9a and 9b mounted on the different memory blocks 10aand 10b in the upper part. Further, similarly also in two memory blocks10c and 10d aligned along the row direction in the lower part, a singlefirst selected gate line 108b is connected to the two PMOS transistors9c and 9d, and a predetermined gate voltage can be configured to beequally applied to the two PMOS transistors 9c and 9d from the shared,first selected gate line 108b.

On the other hand, in the exemplary embodiment, the source line 5aforming a part of the memory cell column wiring 2a is formed by a higherorder source line 12a and two lower order source lines 13a and 13c. Thehigher order source line 12a is provided with a plurality of NMOStransistors 15a and 15c, while the single lower order source line 13a,13c is connected to each NMOS transistor 15a, 15c.

It should be noted that in FIG. 1, as with another source line 5b, ahigher order source line 12b is provided with a plurality of NMOStransistors 15b and 15d, while a single lower order source line 13b, 13dis connected to each NMOS transistor 15b, 15d as a second semiconductorswitch. In the exemplary embodiment, the memory cell column wiring 2a isdisposed so that the higher order bit line 7a, the lower order bit line8a, the higher order source line 12a and the lower order source line 13aare all extended in the column direction while the plural word lines102a to 102d extended in the row direction intersect with the higherorder bit line 7a, the lower order bit line 8a, the higher order sourceline 12a and the lower order source line 13a.

Here, the NMOS transistor 15a, disposed as the second semiconductorswitch between the higher order source line 12a and the lower ordersource line 13a, is connected at the source thereof to the higher ordersource line 12a while being connected at the drain thereof to the lowerorder source line 13a, and is also connected at the gate thereof to asecond selected gate line 113a extended in the row direction. The secondselected gate line 113a is connected to the NMOS transistors 15a and 15bthat are respectively mounted on the memory blocks 10a and 10b alignedalong the row direction in the upper part.

Thus, a predetermined gate voltage can be configured to be equallyapplied from the shared, single second selected gate line 113a to thetwo NMOS transistors 15a and 15b mounted on the different memory blocks10a and 10b in the upper part. Further, similarly also on the two memoryblocks 10c and 10d aligned along the row direction in the lower part, asingle second selected gate line 113b is connected to two NMOStransistors 15c and 15d, and a predetermined gate voltage can beconfigured to be equally applied to the two NMOS transistors 15c and 15dfrom the shared, second selected gate line 113b.

The memory cell transistors 103, provided between the bit line 4a andthe source line 5a, are N-channel memory cell transistor formed with anNMOS structure. Each memory cell transistor 103 is connected at oneterminal thereof to the lower order bit line 8a while being connected atthe other terminal thereof to the lower order source line 13a, and isfurther connected at the gate thereof to, for instance, the word line102a. Incidentally, all the memory cell transistors 103 have the samestructure that a channel region is disposed between one terminal and theother terminal on a semiconductor substrate, and a charge accumulationlayer, an interlayer insulation layer and a control gate aresequentially laminated through a tunnel insulation layer on the channelregion. Thus, the memory cell transistors 103 can be configured toaccumulate electric charges into the charge accumulation layer orextracting electric charges accumulated into the charge accumulationlayer by means of voltage to be applied to the channel region and thecontrol gate.

The non-volatile semiconductor memory device 1 thus structured iscapable of: writing data by accumulating electric charges into only thecharge accumulation layer of a desired one of the memory celltransistors 103 through a data writing action; reading data written in apredetermined one of the memory cell transistors 103; and furthererasing data by extracting electric charges from the charge accumulationlayers of such memory cell transistors 103. Explanation will behereinafter sequentially made for a data writing action, a data readingaction and a data erasing action in the non-volatile semiconductormemory device 1.

It should be noted that in the non-volatile semiconductor memory device1 according to the exemplary embodiment of the present invention, a datawritten state is defined to be a state that electric charges areaccumulated into the charge accumulation layer of a predetermined one ofthe memory cell transistors 103 and data is configured to be erased byextracting the electric charges accumulated into the charge accumulationlayer. However, the present invention is not limited to this, and in thenon-volatile semiconductor memory device 1, the data written state maybe defined to be a state that no electric charge is accumulated into thecharge accumulation layer of a predetermined one of the memory celltransistors 103 and data may be configured to be erased by accumulatingelectric charges into the charge accumulation layer.

(1-2) Data Writing Action in Non-Volatile Semiconductor Memory Device

FIG. 2, shown with the same reference signs assigned to componentscorresponding to those in FIGS. 1 and 6, indicates voltage values in therespective positions of the non-volatile semiconductor memory device 1,where the memory block 10a is set as a selected block 117; the memorycell transistor 103 disposed in the first row of the selected block 117is set as a selected memory cell transistor 115; and all the othermemory blocks 10b, 10c and 10d are set as non-selected blocks 118.

Actually, in the non-volatile semiconductor memory device 1, the wordline 102a connected to the gate of the selected memory cell transistor115 is set as a selected word line 120, and a writing gate voltage of12[V] can be applied to the selected word line 120. Further, in thenon-volatile semiconductor memory device 1, a writing prevention gatevoltage of 4[V] less than the writing gate voltage can be applied to theremaining non-selected word lines 121 except for the selected word line120 in the selected block 117.

Further, at this time, in the non-volatile semiconductor memory device1, a writing voltage of 0[V] (charge accumulating voltage) is applied tothe higher order source line 12a of a memory cell column wiring 18a,i.e., the memory cell column wiring in which the selected memory celltransistor 115 is disposed (hereinafter referred to as a selected memorycell column wiring), while a voltage of 0[V] can be also applied to thehigher order bit line 7a of the selected memory cell wiring 18a. Andfurther in the non-volatile semiconductor memory device 1, a voltage of8[V] is applied to the higher order source line 12b of a memory cellcolumn wiring 18b, i.e., the memory cell column wiring in which only thenon-selected blocks 118 are disposed (hereinafter referred to as anon-selected memory cell wiring), while a writing prevention voltage of8[V] (charge accumulating prevention voltage) can be applied to thehigher order bit line 7b of the non-selected memory cell column wiring18b.

In addition to this, in the non-volatile semiconductor memory device 1,a P-side gate voltage of 0[V] (first gate voltage) can be configured tobe applied to the first selected gate line 108a shared with the selectedblock 117 in the same row (hereinafter referred to as a selected blockrow). Accordingly, in the non-selected memory cell column wiring 18b,the PMOS transistor 9b to which the writing prevention voltage of 8[V]is being applied from the higher order bit line can be switched on.

Thus, in the non-volatile semiconductor memory device 1, with the PMOStransistor 9b in the non-selected memory cell column wiring 18b beingswitched on, the writing prevention voltage of 8[V] can be appliedthrough the PMOS transistor 9b to the lower order bit line 8b of thenon-selected memory cell column wiring 18b intersecting with theselected word line 120. At this time, in the non-selected memory cellcolumn wiring 18b, the NMOS transistor 15b is switched off while avoltage of 8[V] is applied thereto from the higher order source line 12band a voltage of 8[V] is applied thereto from the second selected gateline 113a, and the potential of the lower order source line 13b will bethe same as that of the lower order bit line 8b.

Accordingly, as to a non-selected memory cell transistor 116, i.e., thememory cell transistor at which the selected word line 120 and the lowerorder bit line 8b of the non-selected memory cell column wiring 18bintersect with each other, the writing prevention voltage of 8[V] isapplied to one terminal thereof through the PMOS transistor 9b from thehigher order bit line 7b of the non-selected memory cell column wiring18b, although the high gate voltage of 12[V] is applied to the gatethereof from the selected word line 120. Therefore, a voltage differenceis reduced between the control gate and the channel region, and electriccharges cannot be injected into the charge accumulation layer from thechannel region without occurrence of a quantum tunneling effect.

Thus, the PMOS transistor 9b is used as the first semiconductor switchin the present invention. Therefore, unlike a case of using an NMOStransistor, the PMOS transistor 9b can be switched on even when theP-side gate voltage of 0[V], which is less than the writing preventionvoltage of 8[V] to be applied to the source thereof from the higherorder bit line 7b, is applied from the first selected gate line 108a.Thus, in the non-volatile semiconductor memory device 1, with use of thePMOS transistor 9b as a switch for applying the writing preventionvoltage to the lower order bit line 8b of the non-selected memory cellcolumn wiring 18b intersecting with the selected word line 120, theP-side gate voltage for switching on the PMOS transistor 9b can bereduced than the writing prevention voltage and the voltage of theentire device can be configured to be reduced by that much.

Further, at this time, in the non-volatile semiconductor memory device1, with the application of the voltage of 8[V] as an N-side gate voltage(second gate voltage) to the second selected gate line 113a shared inthe selected block row, the N-side gate voltage can be applied to thegate of the NMOS transistor 15a in the selected memory cell columnwiring 18a. The NMOS transistor 15a in the selected memory cell columnwiring 18a is switched on when the writing voltage of 0[V] is applied tothe source thereof from the higher order source line 12a of the selectedmemory cell column wiring 18a while the N-side gate voltage of 8[V] isapplied to the gate thereof from the second selected gate line 113a.

Thus, in the non-volatile semiconductor memory device 1, the writingvoltage of 0[V] can be applied through the NMOS transistor 15a to thelower order source line 13a of the selected memory cell column wiring18a intersecting with the selected word line 120. At this time, in theselected memory cell column wiring 18a, the voltage of 0[V] is appliedto the PMOS transistor 9a from the higher order bit line 7a, while thevoltage of 0[V] is applied to the PMOS transistor 9a from the firstselected gate line 108a. Therefore, the PMOS transistor 9a can beswitched off and the lower order bit line 8a can be turned into afloating state.

Accordingly, as to the selected memory cell transistor 115 at which theselected word line 120 and the lower order source line 13a of theselected memory cell column wiring 18a intersect with each other, thehigh voltage of 12[V] as a gate voltage is applied to the gate thereoffrom the selected word line 120, while the writing voltage of 0[V] isapplied to the other terminal thereof from the lower order source line13a through the NMOS transistor 15a in the selected memory cell columnwiring 18a. Therefore, a voltage difference is increased between thecontrol gate and the channel region. As a result, a quantum tunnelingeffect occurs and electric charges can be injected into the electriccharge layer from the channel region.

And thus, in the non-volatile semiconductor memory device 1 according tothe present invention, the writing prevention voltage is configured tobe applied, with the PMOS transistor 9b being switched on. Aside fromthis, the writing voltage is configured to be applied, with the NMOStransistor 15a being switched on. Therefore, the P-side gate voltage andthe N-side gate voltage can be separately set to have voltage valuesfalling between the writing prevention voltage value and the writingvoltage value so that the PMOS transistor 9b and the NMOS transistor 15acan be thereby switched on, and even, can be set to have voltage valuesless than those in a conventional device.

Incidentally, in the non-selected blocks 118 located in the row alongwhich only the non-selected blocks 118 are aligned (hereinafter referredto as a non-selected block row), a P-side gate voltage of 8[V] isapplied to the first selected gate line 108b shared by the non-selectedblocks 118, and all the PMOS transistors 9c and 9d connected to thefirst selected gate line 108b can be equally switched off. Further inthe non-selected blocks 118 located in the non-selected block row, avoltage of 0[V] is applied to the second selected gate line 113b sharedby the non-selected blocks 118, and all the NMOS transistors 15c and 15dconnected to the second selected gate line 113b can be equally switchedoff.

It should be noted in the non-volatile semiconductor memory device 1, avoltage of 0[V] is applied to the respective non-selected word lines 121in the non-selected block row, while no voltage is applied to therespective non-selected memory cell transistors 116 of the non-selectedblocks 118 in the non-selected block row. Therefore, a quantum tunnelingeffect does not occur in all the non-selected memory cell transistors116 and electric charges are not injected into the charge accumulationlayers from the channel regions.

Thus, in the non-volatile semiconductor memory device 1, data writingcan be executed by accumulating electric charges into only the chargeaccumulation layer of the selected memory cell transistor 115 at whichthe selected word line 120 and the lower order source line 13a of theselected memory cell column wiring 18a intersect with each other, whiledata writing can be prevented without accumulating electric charges intothe charge accumulation layers of all the other non-selected memory celltransistors 116.

(1-3) Data Reading Action in Non-Volatile Semiconductor Memory Device

Here, in such non-volatile semiconductor memory device 1, data writtenin the selected memory cell transistor 115 can be read out therefrom asfollows. Incidentally, as with FIG. 3 shown with the same referencesigns assigned to components corresponding to those in FIG. 2,explanation will be hereinafter made where the memory cell transistor103, which is disposed in the first row of, for instance, the memoryblock 10a in the first column and first row position among the fourmemory blocks 10a, 10b, 10c and 10d of the non-volatile semiconductormemory device 1, is defined as a readout memory cell transistor 20 forreading out data while all the other remaining memory cell transistors103 are defined as non-readout memory cell transistors 21.

It should be herein noted that among the memory blocks 10a, 10b, 10c and10d, the memory block 10a on which the readout memory cell transistor 20is disposed is referred to as a readout block 22a while the otherremaining memory blocks 10b, 10c and 10d are referred to as non-readoutblocks 23. Further, the memory cell column wiring 2a in which thereadout memory cell transistor 20 is disposed is herein referred to as aselected memory cell column wiring (readout memory cell column wiring)18a.

Actually, in the non-volatile semiconductor memory device 1, a fixedvoltage of 2[V] can be applied to the higher order source line 12a ofthe selected memory cell column wiring 18a and the higher order sourceline 12b of the non-selected memory cell column wiring (non-readoutmemory cell column wiring) 18b, while a pre-charge voltage of 3[V] canbe applied to the higher order bit line 7a of the selected memory cellcolumn wiring 18a. Further, a fixed voltage of 2[V] can be applied tothe higher order bit line 7b of the non-selected memory cell columnwiring 18b. In the non-volatile semiconductor memory device 1, a P-sidegate voltage of 0[V] is applied to the first selected gate line 108ashared in the row in which the readout block 22a is located (hereinafterreferred to as a readout block row).

In other words, as to the PMOS transistor 9a on the readout block 22a,for instance, the pre-charge voltage of 3[V] is applied to the sourcethereof from the higher order bit line 7a, while the P-side gate voltageof 0[V] is applied to the gate thereof from the first selected gate line108a. As a result, the PMOS transistor 9a can be switched on. Thus, inthe readout block 22a, the pre-charge voltage of 3[V] can be appliedfrom the higher order bit line 7a to the lower order bit line 8a throughthe PMOS transistor 9a, and the pre-charge voltage can be applied to oneends of the memory cell transistors 103 connected to the lower order bitline 8a.

At this time, an N-side gate voltage of 3[V] can be applied to thesecond selected gate line 113a shared in the readout block row.Accordingly, as to the NMOS transistor 15a in the readout block row, thefixed voltage of 2[V] is applied to the source thereof from the higherorder source line 12a, while the N-side gate voltage of 3[V] is appliedto the gate thereof from the second selected gate line 113a. As aresult, the NMOS transistor 15a can be switched on. Thus, on the readoutblock 22a, the fixed voltage of 2[V] can be applied from the higherorder source line 12a to the lower order source line 13a through theNMOS transistor 15a, and the fixed voltage can be applied to the otherends of the memory cell transistors 103 connected to the lower ordersource line 13a.

On the other hand, a readout gate voltage of 2[V] cab be applied to theselected word line 120 connected to the gate of the readout memory celltransistor 20, while a readout prevention gate voltage of 0[V] lowerthan the readout gate voltage can be applied to the remainingnon-selected word lines 121 other than the selected word line 120. Thus,as to the readout memory cell transistor 20, the pre-charge voltage of3[V] can be applied to one end thereof from the higher order bit line 7athrough the PMOS transistor 9a while the fixed voltage of 2[V] can beapplied to the other end thereof from the higher order source line 12athrough the NMOS transistor 15a, and further, the readout gate voltageof 2[V] can be applied thereto from the selected word line 120.

When electric charges has been herein accumulated into the chargeaccumulation layer of the readout memory cell transistor 20 and thusdata has been written therein, the readout memory cell transistor 20remains in the off state while being affected by the electric chargesaccumulated into the charge accumulation layer, even when the readoutgate voltage is applied to the control gate thereof. Accordingly, thepre-charge voltage of 3[V] can be maintained without change in thehigher order bit line 7a. In comparison with this, when no electriccharge has been accumulated into the charge accumulation layer of thereadout memory cell transistor 20 and thus no data has been writtentherein, the readout memory cell transistor 20 is switched on by meansof the readout gate voltage applied to the control gate thereof, withoutbeing affected by electric charges in the charge accumulation layer.Accordingly, the pre-charge voltage of 3[V] can vary in the higher orderbit line 7a by the amount of electric current flowing through thereadout memory cell transistor 20.

It should be noted that at this time, in the row in which only thenon-readout blocks 23 are aligned (hereinafter referred to as anon-readout block row), a P-side gate voltage of 3[V] equal to thepre-charge voltage is applied to the respective PMOS transistors 9c and9d from the first selected gate line 108b, and thereby, the PMOStransistors 9c and 9d can be switched off. Thus, on the non-readoutblock row, the voltages from the higher order bit lines 7a and 7b areblocked by the PMOS transistors 9c and 9d. Accordingly, the voltagescannot be applied to the non-readout memory cell transistors 21 disposedin the lower order bit lines 8c and 8d connected to the PMOS transistors9c and 9d.

Thus, the pre-charge voltage to be applied to the higher order bit line7a can be configured to be applied to only the readout memory celltransistor 20 from which data is intended to be read out in the selectedmemory cell column wiring 18a. It should be noted that in thenon-readout block row, an N-side gate voltage of 3[V] is applied to thesecond selected gate line 113b. Accordingly, the NMOS transistors 15cand 15d are switched on, and the fixed voltage is applied without changeto the lower order source line 13c from the higher order source line12a.

Thus, in the non-volatile semiconductor memory device 1, it can beconfigured to be determined whether or not data has been written in thereadout memory cell transistor 20 by measuring the pre-charge voltage ofthe higher order bit line 7a, which varies depending on whether or notelectric charges are accumulated into the charge accumulation layer ofthe readout memory cell transistor 20.

It should be noted that this example describes a case of setting apre-charge voltage to be 3[V] and of determining whether or not thepre-charge voltage is reduced towards the fixed voltage applied to thesource due to the data in the memory cell transistor. However, thepre-charge voltage is not necessarily higher than the fixed voltage. Forexample, it is also possible to determine whether or not data has beenwritten in the readout memory cell transistor 20 by variously settingthe pre-charge voltage to 0[V], 1[V] or etc. and by determining whetheror not the pre-charge voltage is increased towards the fixed voltage.

(1-4) Data Erasing Action of Non-Volatile Semiconductor Memory Device

Next, explanation will be hereinafter made for the data erasing actionin the non-volatile semiconductor memory device 1. FIG. 4, shown withthe same reference signs assigned to components corresponding to thosein FIG. 1, is a schematic diagram showing a split well structure formedon a deep N-well DNW (not shown in the figure) in addition to thecircuit configuration of the non-volatile semiconductor memory device 1.

In the non-volatile semiconductor memory device 1, the memory blocks 10aand 10b aligned along the row direction in the upper part and the memoryblocks 10c and 10d aligned along the row direction in the lower part areherein formed in different unit well structures W1 and W2, respectively.It should be noted that the unit well structures W1 and W2 have the samestructure, and therefore, explanation will be hereinafter made byfocusing on one of them, i.e., the unit well structure W1. For example,in the unit well structure W1, the memory cell transistors 103 and theNMOS transistors 15a and 15b are formed on a single P-well PW1, whilethe PMOS transistors 9a and 9b are formed on a single N-well.

Such non-volatile semiconductor memory device 1 can be configured toexecute a data erasing action for each of the substrates of the P-wellsPW1 and PW2. It should be herein noted that explanation will behereinafter made for a case of erasing the data in the memory blocks 10aand 10b formed in the unit well structure W1 in the upper part and ofretaining the data, without erasing it, in the memory blocks 10c and 10dformed in the unit well structure W2 in the lower part. It should benoted that the plural memory blocks 10a and 10b from which data iserased will be collectively referred to as an erasing block, whereas theplural memory blocks 10c and 10d in which the data is retained withoutbeing erased will be collectively referred to as a non-erasing block.

In this case, on the erasing block, an erasing voltage of 9[V] can beapplied to the P-well PW1 of the unit well structure W1, while a voltageof 9[V] can be also applied to an N-well NW1. Further, on the erasingblock, a P-side gate voltage of 9[V] is applied to the shared, firstselected gate line 108a, and thereby, the PMOS transistors 9a and 9b areswitched off. Further, on the erasing block, a voltage of 0[V] isapplied to the second selected gate line 113a, and thereby, the NMOStransistors 15a and 15b are also switched off. Further, a gate voltageof 0[V] can be applied to all the word lines 102a to 102d.

Hereby, on the erasing block, the erasing voltage of 9[V] is applied tothe P-well PW1, while the voltage of 0[V] is applied to the control gateopposed to the P-well PW1. Therefore, the voltage of the P-well PW1 canbe higher than that of the control gate. Thus, on the erasing block,electric charges accumulated into the charge accumulation layers of thememory cell transistors 103 are attracted to the P-well PW1 to whichhigher voltage is applied, and are taken out of the charge accumulationlayers. Data can be thereby configured to be erased. Thus, the erasingblock can be configured to collectively erase data from all the memorycell transistors 103 formed on the P-well PW1.

On the other hand, on the non-erasing block in which data is retainedwithout being erased in the lower part, similarly to the erasing block,the PMOS transistors 9c and 9d can be switched off while a P-side gatevoltage of 9[V] is applied to the first selected gate line 108b;similarly, the NMOS transistors 15c and 15d can be switched off while avoltage of 0[V] is applied to the second selected gate line 113b; andfurther, a gate voltage of 0[V] can be applied to all the word lines102e to 102h. In addition to this, on the non-erasing block, unlike theerasing block, an erasing prevention voltage of 0[V] can be configuredto be applied to the P-well PW2.

Accordingly, on the non-erasing block, no voltage difference is producedbetween the control gates of the memory cell transistors 103 and theP-well PW2; electric charges accumulated into the charge accumulationlayers of the memory cell transistors 103 are retained in an unchangedcondition without being attracted to the P-well PW2; and thereby, thedata written state can be maintained. Thus, in the non-volatilesemiconductor memory device 1, through the regulation of the voltages ofthe P-wells PW1 and PW2, data can be erased from a desired erasingblock, while data can be retained in an unchanged condition withoutbeing erased from the non-erasing block other than the erasing block.

(1-5) Action and Effect

In the non-volatile semiconductor memory device 1 with theaforementioned configuration, the memory cell transistors 103 aredisposed in a row and column matrix with respect to the plural memorycell column wirings 2a and 2b and the plural word lines 102a to 102h,and data can be written in the selected memory cell transistor 115 atwhich the selected word line 120 and the selected memory cell columnwiring 18a intersect with each other based on the voltage differencebetween the voltage of the predetermined, selected word line 120 andthat of the predetermined, selected memory cell column wiring 18a.

Here, in the non-volatile semiconductor memory device 1 according to thepresent invention, the PMOS transistors 9a, 9b, 9c and 9d forcontrolling voltage application to the memory cell transistors 103 aremounted on the memory cell column wirings 2a and 2b. In accumulatingelectric charges into the selected memory cell transistor 115 among thememory cell transistors 103 in order to write data in the selectedmemory cell transistor 115, the PMOS transistor 9b, to which the writingprevention voltage of the non-selected memory cell column wiring 18b isapplied, is configured to be switched on by means of the P-side gatevoltage and the writing prevention voltage is configured to be appliedto the non-selected memory cell transistor 116 that intersects with theselected word line 120.

At this time, in the non-volatile semiconductor memory device 1, thePMOS transistor 9b can be switched on by applying thereto a P-side gatevoltage that is lower than the writing prevention voltage to be appliedto the non-selected memory cell column wiring 18b by a threshold voltage|V_(thp)| of the PMOS transistor 9b. Therefore, the P-side gate voltagecan be set to be lower than the writing prevention voltage, andreduction in voltage can be achieved by that much in executing a datawriting action.

Further, in the present non-volatile semiconductor memory device 1, theP-side gate voltage to be applied to the first selected gate line 108ais adjusted to have a voltage value (of 0[V] in this case) greater thanor equal to that of the voltage to be applied to the higher order bitline 7a of the selected memory cell column wiring 18a. Therefore, anelectric field to be applied to the gate insulating film can be relaxedby switching on the PMOS transistor 9b in the non-selected memory cellcolumn wiring 18b, and simultaneously, by switching off the PMOStransistor 9a in the selected memory cell column wiring 18a, and furtherby reducing the voltage difference between the substrate and the gate inthe PMOS transistor 9a.

Further, the present non-volatile semiconductor memory device 1 isdesigned such that the NMOS transistors 15a, 15b, 15c and 15d forcontrolling voltage application to the memory cell transistors 103 aremounted on the memory cell column wirings 2a and 2b aside from the PMOStransistors 9a, 9b, 9c and 9d. And in the non-volatile semiconductormemory device 1, when data is written in the selected memory celltransistor 115, the N-side gate voltage is configured to be applied tothe NMOS transistor from the second selected gate line 113a aside fromthe P-side gate voltage to be applied to the PMOS transistor 9b. TheNMOS transistor in the selected memory cell column wiring is therebyswitched on, and the writing voltage is accordingly configured to beapplied to the selected memory cell transistor 115 from the NMOStransistor 15a.

Thus, in the non-volatile semiconductor memory device 1, the P-side gatevoltage for switching on the PMOS transistor 9b and the N-side gatevoltage for switching on the NMOS transistor 15a can be respectively setto have low voltage values capable of switching on the transistors 9band 15a. Hence, it is possible to obtain flexible settings such asreduction in voltage in accumulating electric charges into the selectedmemory cell transistor 115 in comparison with a conventional device.

Further, in the present non-volatile semiconductor memory device 1, theN-side gate voltage is configured to be separately applied to the NMOStransistor 15a in the selected memory cell column wiring 18a from thesecond selected gate line 113a. With the configuration, the N-side gatevoltage can be variously adjusted to be a low voltage capable ofswitching on the NMOS transistor 15a without being constrained by thevoltage value of the P-side gate voltage to be applied to the PMOStransistor 9a. In the present non-volatile semiconductor memory device1, the N-side gate voltage to be applied to the second selected gateline 113a is adjusted to have a voltage value (of 8[V] in this case)less than or equal to that of the voltage to be applied to the higherorder source line 12b of the non-selected memory cell column wiring 18b.Therefore, an electric field to be applied to the gate insulating filmof the NMOS transistor 15b can be relaxed by switching on the NMOStransistor 15a in the selected memory cell column wiring 18a, andsimultaneously, by switching off the NMOS transistor 15b in thenon-selected memory cell column wiring 18b, and further by reducing thevoltage difference between the substrate and the gate in the NMOStransistor 15b.

Actually, in the present exemplary embodiment, the non-volatilesemiconductor memory device 1 is designed such that the PMOS transistor9a is mounted between the higher order bit line 7a and the lower orderbit line 8a in the memory block 10a while the NMOS transistor 15a isdesigned between the higher order source line 12a and the lower ordersource line 13a.

Further, the memory blocks 10a, 10b, 10c and 10d are respectivelydesigned to have such structure. Hence, in the non-volatilesemiconductor memory device 1, when data is written in the selectedmemory cell transistor 115, the writing prevention voltage can beapplied to the non-selected memory cell transistor 116 from the PMOStransistor 9b of the non-selected memory cell column wiring 18b throughthe lower order bit line 8b while the PMOS transistor 9b is beingswitched on. And simultaneously with this, in the selected memory cellcolumn wiring 18a, the writing voltage can be applied to the selectedmemory cell transistor 115 from the NMOS transistor 15a through thelower order source line 13a while the NMOS transistor 15a is beingswitched on.

Here, in the non-volatile semiconductor memory device 1, the writinggate voltage of 12[V] is applied as V_(W1) to the selected word line 120while the writing prevention gate voltage of 4[V] is applied as V_(W2)to the non-selected word lines 121. Thus, V_(W1)−V_(W2)<9[V] is set as avoltage condition and a voltage difference to be controlled by theperipheral circuit of the word lines 102a to 102h is set to be less than9[V]. Hence, MOS transistors (not shown in the figures), respectivelyincluding a gate insulating layer with a thickness of less than 13 [nm],can be used in the peripheral circuit without using special MOStransistors respectively having a gate insulating layer with a largethickness in the peripheral circuit.

Further, in the non-volatile semiconductor memory device 1, the writingprevention voltage of 8[V] is applied as V_(B1) to the higher order bitline 7b of the non-selected memory cell column wiring 18b, while thewriting voltage of 0[V] is applied as V_(B2) to the higher order bitline 7a of the selected memory cell column wiring 18a. Thus,V_(B1)−V_(B2)<9[V] is set as a voltage condition and a voltagedifference to be controlled by the peripheral circuit of the higherorder bit lines 7a and 7b is set to be less than 9[V]. Hence, MOStransistors (not shown in the figures), respectively including a gateinsulating layer with a thickness of less than 13 [nm], can be used inthe peripheral circuit without using special MOS transistorsrespectively having a gate insulating layer with a large thickness inthe peripheral circuit.

Further, in the non-volatile semiconductor memory device 1, the writingprevention voltage of 8[V] is applied as V_(B1) to the higher order bitline 7b of the non-selected memory cell column wiring 18b, and the gatevoltage of the PMOS transistor 9a is adjusted. A gate-to-substratevoltage V_(GW) of the PMOS transistor 9b is thereby set to be lower thanthe writing prevention voltage. Hence, V_(B1)>V_(GW) can be set as avoltage condition. Thus, in the non-volatile semiconductor memory device1, it is possible to suppress the voltage to be applied to the PMOStransistor 9b, and to form the gate insulating layer with a filmthickness of less than 13 [nm] between the gate and the semiconductorsubstrate in the PMOS transistor 9b.

Here, when the PMOS transistors 9a and 9b are switched on while a gatevoltage of 7[V] is applied thereto where the substrate voltages thereofare both set to be 8[V], the gate-to-substrate voltages of the PMOStransistors 9a and 9b become 1[V], and electric fields to be applied tothe gate insulating films of the PMOS transistors 9a and 9b can beremarkably reduced. Similarly, when the NMOS transistors 15a and 15b areswitched on while a gate voltage of 1[V] is applied thereto where thesubstrate voltages thereof are both set to be 0V, the gate-to-substratevoltages of the NMOS transistors 15a and 15b become 1[V], and electricfields to be applied to the gate insulating films of the NMOStransistors 15a and 15b can be remarkably reduced. As a result,reliability of the gate insulating films can be remarkably enhanced. Andthus, in the non-volatile semiconductor memory device 1, voltages to beapplied to the NMOS transistors 15a and 15b can be suppressed.Therefore, it is possible to form the gate insulating film with a filmthickness of less than 13 [nm] between the gate and the semiconductorsubstrate in the NMOS transistor 15a.

In other words, such remarkable relaxation of electric field cannot beachieved when either NMOS transistors or PMOS transistors are configuredto apply both of the writing voltage and the writing prevention voltageas with a conventional device. In comparison with this, in the presentinvention, combinational use of the PMOS transistors and the NMOStransistors can remarkably contribute to enhancement in reliability ofthe gate insulating films.

It should be noted that in the erasing action shown in FIG. 4, the casehas been exemplified that the voltage of 0[V] is applied to the secondselected gate line 113a, and thereby, the gate voltages of the NMOStransistors 15a and 15b are set to be 0[V]. However, the P-well PW1 onthe erasing block is 9[V]. Therefore, rather when the gate voltages ofthe NMOS transistors 15a and 15b formed therein are higher than 0[V],the gate-to-substrate voltages of the NMOS transistors 15a and 15b arelowered and it is thereby possible to reduce electric fields applied tothe gate insulating films of the NMOS transistors 15a and 15b.Therefore, a voltage of 4[V] or etc., for instance, may be applied tothe second selected gate line 113a.

According to the aforementioned configuration, the non-volatilesemiconductor memory device 1 is designed to be provided with the NMOStransistor 15a that is switched on and off by means of the N-side gatevoltage aside from the P-side gate voltage for switching on and off thePMOS transistor 9b configured to apply the writing prevention voltage tothe non-selected memory cell transistor 116 in accumulating electriccharges into the selected memory cell transistor 115, and has a polarityopposite to that of the PMOS transistor 9b.

Accordingly, in the non-volatile semiconductor memory device 1, theP-side gate voltage for switching on the PMOS transistor 9b and theN-side gate voltage for switching on the NMOS transistor 15a can beseparately adjusted, and it is possible to more flexibly set the voltagein accumulating electric charges into the selected memory celltransistor 115, for instance, to reduce the voltage in comparison with aconventional device by respectively setting the P-side gate voltage andthe N-side gate voltage to have voltage values as low as possiblewhereby the PMOS transistor 9a and the NMOS transistor 15a can beswitched on.

Further, in the present non-volatile semiconductor memory device 1, thewriting prevention voltage is configured to be applied to thenon-selected memory cell transistor 116 that intersects with theselected word line 120, while the PMOS transistor 9b, to which thewriting prevention voltage is applied, is switched on. Therefore, theP-side gate voltage in switching on the PMOS transistor 9b can besuppressed to be lower than the writing prevention voltage. The voltagein accumulating electric charges in the selected memory cell transistor115 can be thereby reduced by that much in comparison with aconventional device.

Further, in the non-volatile semiconductor memory device 1, it is alsopossible to variously adjust the N-side gate voltage of the NMOStransistor 15a configured to apply the writing voltage to the selectedmemory cell column wiring 18a to be a low voltage separately from theP-side gate voltage.

Thus, in the present non-volatile semiconductor memory device 1, therole of applying voltage to either the selected memory cell transistor115 or the non-selected memory cell transistor 116 is shared by the PMOStransistor 9b and the NMOS transistor 15a through the configuration ofapplying a high voltage as the writing prevention voltage from the PMOStransistor 9b and of applying a low voltage as the writing voltage fromthe NMOS transistor 15a in accumulating electric charges into theselected memory cell transistor 115. Hence, it is possible to separatelyadjust the gate voltage and the source voltage of the PMOS transistor 9band those of the NMOS transistor 15a, and finally, the gate-to-substratevoltage can be suppressed low.

It should be noted that the aforementioned exemplary embodiment hasdescribed, for instance, the case of applying the memory cell columnwiring 2a in which the higher order bit line 7a, the lower order bitline 8a, the higher order source line 12a and the lower order sourceline 13a are disposed while being directed to the row direction.However, the present invention is not limited to this, and it is allowedto apply any one of various memory cell column wirings in which thehigher order bit line 7a, the lower order bit line 8a, the higher ordersource line 12a and the lower order source line 13a are arbitrarilydisposed in either the column direction or the row direction inaccordance with the arrangement condition of the memory cell transistors103, the PMOS transistor 9a and the NMOS transistor 15a, for instance,including a memory cell column wiring in which higher order source linesare disposed in the row direction perpendicular to the higher order bitline 7a, the lower order bit line 8a and the lower order source line13a.

(1-6) Exemplary Modifications of Writing Action of Non-VolatileSemiconductor Memory Device According to First Exemplary Embodiment

It should be noted that the aforementioned exemplary embodiment hasdescribed the case of applying the non-volatile semiconductor memorydevice 1 as a non-volatile semiconductor memory device configured to:apply an N-side gate voltage greater than or equal to V_(B2)+|V_(thn)|(where V_(B2) is the voltage of the selected memory cell column wiring(writing voltage), while V_(thn) is the threshold voltage of the NMOStransistor) to the NMOS transistor; and apply a P-side gate voltage lessthan or equal to V_(B1)−|V_(thp)| (where V_(B1) is the voltage of thenon-selected memory cell column wiring (writing prevention voltage),while V_(thp) is the threshold voltage of the PMOS transistor) to thePMOS transistor, in writing data in the selected memory cell transistor.The non-volatile semiconductor memory device 1 is herein configured to:apply the N-side gate voltage of 8[V] greater than or equal toV_(B2)+|V_(thn)| to the NMOS transistor 15a; and apply the P-side gatevoltage of 0[V] less than or equal to V_(B1)−|V_(thp)| to the PMOStransistor 9b. However, the present invention is not limited to this. Aslong as the N-side gate voltage to be applied to the NMOS transistor isgreater than or equal to V_(B2)+|V_(thn)| while the P-side gate voltageto be applied to the PMOS transistor is less than or equal toV_(B1)−|V_(thp)|, the N-side gate voltage and the P-side gate voltagemay be variously set to have other voltage values.

Further, the aforementioned exemplary embodiment has explained the casethat V_(W1)−V_(W2)<9[V] (where V_(W1) is the accumulating gate voltageof the selected word line while V_(W2) is the accumulating preventiongate voltage of the non-selected word line) is established as arelational equation in accumulating electric charges into the selectedmemory cell transistor, and the condition that the voltage differencebetween V_(W1) and V_(W2) is less than 9[V] is configured to besatisfied by applying the writing gate voltage of 12[V] as V_(W1) to theselected word line 120 and by applying the writing prevention gatevoltage of 4[V] as V_(W2) to the non-selected word lines 121. However,the present invention is not limited to this. As long as theaforementioned condition of V_(W1)−V_(W2)<9[V] is satisfied, thevoltages to be applied to the selected word line and the non-selectedword line may be set to have various voltage values.

Further, the aforementioned exemplary embodiment has described the casethat V_(B1)−V_(B2)<9[V] (where V_(B1) is the charge accumulatingprevention voltage of the non-selected memory cell column wiring whileV_(B2) is the charge accumulating voltage of the selected memory cellcolumn wiring) is established as a relational equation in accumulatingelectric charges into the selected memory cell transistor, and thecondition that the voltage difference between V_(B1) and V_(B2) is lessthan 9[V] is configured to be satisfied by applying the writingprevention voltage of 8[V] as V_(B1) to the higher order bit line 7b ofthe non-selected memory cell column wiring 18b and by applying thewriting voltage of 0[V] as V_(B2) to the higher order bit line 7a of theselected memory cell column wiring 18a. However, the present inventionis not limited to this. As long as the aforementioned condition ofV_(B1)−V_(B2)<9[V] is satisfied, the voltages to be applied to theselected memory cell column wiring 18a and the non-selected memory cellcolumn wiring 18b may be set to have various voltage values.

Further, the aforementioned exemplary embodiment has described the casethat voltage is applied to the source line of the non-selected memorycell column wiring in accumulating electric charges into the selectedmemory cell transistor, where the voltage, applied to the source line ofthe non-selected memory cell column wiring, is set to have a voltagevalue, which is less than that of the voltage to be applied to the bitline of the non-selected memory cell column wiring and is also greaterthan or equal to that obtained by subtracting the threshold voltageV_(thn) of the NMOS transistor from that of the N-side gate voltage tobe applied to the NMOS transistor. However, the present invention is notlimited to this. For example, any of the following conditions may beconfigured to be satisfied: that voltage is applied to the bit line ofthe selected memory cell column wiring in accumulating electric chargesinto the selected memory cell transistor, where the voltage, applied tothe bit line of the selected memory cell column wiring, is set to have avoltage value, which is greater than that of the voltage to be appliedto the source line of the selected memory cell column wiring and is alsoless than or equal to that obtained by adding the threshold voltageV_(thp) of the PMOS transistor to the P-side gate voltage to be appliedto the PMOS transistor; that the source line of the non-selected memorycell column wiring is set to be in an open state in accumulatingelectric charges into the selected memory cell transistor; and that thebit line of the selected memory cell column wiring is set to be in anopen state in accumulating electric charges into the selected memorycell transistor.

(1-6-1) Writing Action in First Exemplary Modification

For example, in FIG. 5 shown with the same reference signs assigned tocomponents corresponding to those in FIG. 2, a non-volatilesemiconductor memory device 25 is different from the aforementionednon-volatile semiconductor memory device 1 regarding the voltage valueof the P-side gate voltage that switches on the PMOS transistor 9b inthe non-selected memory cell column wiring 18b in data writing and thatof the N-side gate voltage that switches on the NMOS transistor 15a inthe selected memory cell column wiring 18a in data writing.

Incidentally, similarly to FIG. 2, FIG. 5 shows voltages in therespective positions, for instance, where the block in the first columnand first row position is set as the selected block 117 and only thememory cell transistor 103 in the first row of the selected block 117 isset as the selected memory cell transistor 115, while the other blocksare set as the non-selected blocks 118.

Actually, when a data writing action is executed, in the non-volatilesemiconductor memory device 25, a P-side gate voltage of less than 8[V]can be applied to the first selected gate line 108a shared in theselected block row. The voltage value of less than 8[V] of the P-sidegate voltage V_(GP) is herein the one set based on a writing preventionvoltage of 8[V] to be applied to the higher order bit line 7b of thenon-selected memory cell column wiring 18b and a threshold voltageV_(thp) of the PMOS transistor 9b in the non-selected memory cell columnwiring 18b, and is also the one (e.g., 7[V]) set under a condition ofswitching on the PMOS transistor 9b, i.e., a condition of writingprevention voltage of 8[V]−|V_(thp)|>V_(GP).

The PMOS transistor 9b, to the source of which the writing preventionvoltage of 8[V] is applied from the higher order bit line 7b of thenon-selected memory cell column wiring 18b, is switched on when theP-side gate voltage V_(GP) of less than 8[V] is applied thereto, and thewriting prevention voltage of 8[V] can be applied to the lower order bitline 8b of the non-selected memory cell column wiring 18b intersectingwith the selected word line 120. At this time, as to the non-selectedmemory cell column wiring 18b, a voltage of 8[V] is being applied to theNMOS transistor 15b from the higher order source line 12b, while avoltage of 1[V] is being applied to the NMOS transistor 15b from thesecond selected gate line 113a. Therefore, the NMOS transistor 15b isswitched off and the electric potential of the lower order source line13b becomes the same as that of the lower order bit line 8b.

Accordingly, as to the non-selected memory cell transistor 116 at whichthe selected word line 120 and the lower order bit line 8b of thenon-selected memory cell column wiring 18b intersect with each other,the writing prevention voltage of 8[V] is applied to one terminalthereof from the higher order bit line 7b of the non-selected memorycell column wiring 18b through the PMOS transistor 9b, although a highvoltage of 12[V] as a gate voltage is applied to the control gatethereof from the selected word line 120. Therefore, a voltage differenceis reduced between the control gate and the channel region, and electriccharges cannot be injected into the charge accumulation layer from thechannel region without occurrence of a quantum tunneling effect.

Further, at this time, in the non-volatile semiconductor memory device25, an N-side gate voltage of greater than 0[V] can be applied to thesecond selected gate line 113a shared in the selected block row. Thevoltage of greater than 0[V] of the N-side gate voltage V_(GN) is hereinthe one set based on a writing voltage of 0[V] to be applied to thehigher order source line 12a of the selected memory cell column wiring18a and a threshold voltage V_(thn) of the NMOS transistor 15a in theselected memory cell column wiring 18a, and is also the one (e.g., 1[V])set under a condition of switching on the NMOS transistor 15a, i.e., acondition of writing prevention voltage of 0[V]+|V_(thn)|<V_(GN).

The NMOS transistor 15a, to the source of which the writing voltage of0[V] is applied from the higher order source line 12a of the selectedmemory cell column wiring 18a, is switched on when the N-side gatevoltage V_(GN) of greater than 0[V] is applied thereto, and the writingvoltage of 0[V] can be applied to the lower order source line 13a of theselected memory cell column wiring 18a intersecting with the selectedword line 120. At this time, as to the selected memory cell columnwiring 18a, a voltage of 0[V] is being applied to the PMOS transistor 9afrom the higher order bit line 7a, while the voltage of 7[V] is beingapplied to the PMOS transistor 9a from the first selected gate line108a. Therefore, the PMOS transistor 9a is switched off and the electricpotential of the lower order bit line 8a becomes the same as that of thelower order source line 13a to which the writing voltage is beingapplied.

Thus, as to the selected memory cell transistor 115 at which theselected word line 120 and the lower order source line 13a of theselected memory cell column wiring 18a intersect with each other, thehigh voltage of 12[V] as the gate voltage is applied to the control gatethereof from the selected word line 120, while the writing voltage of0[V] is applied to the other terminal thereof from the lower ordersource line 13a through the NMOS transistor 15a in the selected memorycell column wiring 18a. Accordingly, in the selected memory celltransistor 115, a voltage difference is increased between the controlgate and the channel region, and as a result, a quantum tunneling effectoccurs and electric charges can be injected into the charge accumulationlayer from the channel region.

Thus, even in the non-volatile semiconductor memory device 25, theP-side gate voltage to be applied to the first selected gate line 108acan be remarkably reduced in comparison with a conventional device,while the N-side gate voltage to be applied to the second selected gateline 113a can be remarkably reduced in comparison with the conventionaldevice.

(1-6-2) Writing Action in Second Exemplary Modification

Another non-volatile semiconductor memory device may be configured suchthat, in a data writing action, the same voltage value may be set forthe P-side gate voltage for switching on the PMOS transistor 9b of thenon-selected memory cell column wiring 18b and the N-side gate voltagefor switching on the NMOS transistor 15a of the selected memory cellcolumn wiring 18a.

For example, in the non-volatile semiconductor memory device, the P-sidegate voltage and the N-side gate voltage, having the same voltage value,can be applied to the PMOS transistor 9b and the NMOS transistor 15a,respectively, from the same voltage generating source, and thus, meansfor applying voltage may be shared by the PMOS transistor 9b and theNMOS transistor 15a. In this case, due to the shared means for applyingvoltage, the entire device configuration can be simplified by that much.

For example, in such non-volatile semiconductor memory device, theP-side gate voltage to be applied to the PMOS transistor 9b can be setto be 4[V], while the N-side gate voltage to be applied to the NMOStransistor 15a can be also set to be 4[V]. Therefore, the P-side gatevoltage and the N-side gate voltage can be remarkably reduced in awriting action in comparison with the aforementioned non-volatilesemiconductor memory device 1. Further, in comparison with theaforementioned non-volatile semiconductor memory device 1, a voltagedifference can be eliminated between the both voltages by setting thesame voltage value for the both voltages. Therefore, the voltageamplitude for the entire device can be reduced by that much.

It should be noted that in the present invention, different sets ofmeans for applying voltage may be configured to separately applyvoltages to the first selected gate line 108a and the second selectedgate line 113a, even when the P-side gate voltage to be applied to thePMOS transistor 9a and the N-side gate voltage to be applied to the NMOStransistor 15a have the same voltage value.

In the present invention, various voltages may be applied to the higherorder bit line 7a as long as the PMOS transistor 9a in the selectedmemory cell column wiring 18a can be switched off. On the other hand,various voltages may be applied to the higher order source line 12b aslong as the NMOS transistor 15b in the non-selected memory cell columnwiring 18b can be switched off.

The PMOS transistor 9a in the selected memory cell column wiring 18a maybe switched off by applying, for instance, a selected bit voltage V_(B2)of 4[V] to the higher order bit line 7a of one selected memory cellcolumn wiring 18a, whereas the NMOS transistor 15b in the non-selectedmemory cell column wiring 18b may be switched off by applying, forinstance, a non-selected source voltage V_(B1) of 4[V] to the higherorder source line 12b of the other non-selected memory cell columnwiring 18b.

The selected bit voltage V_(B2) is the one set for satisfying acondition that the voltage value thereof is greater than or equal tothat of the writing voltage to be applied to the higher order sourceline 12a of the selected memory cell column wiring 18a while being lessthan or equal to that obtained by adding a threshold voltage |V_(thp)|of the PMOS transistor 9a to a P-side gate voltage V_(GP) to be appliedto the PMOS transistor 9a of the selected memory cell column wiring 18a(i.e., less than or equal to (V_(GP)+|V_(thp)|)).

On the other hand, the non-selected source voltage V_(s1) is the one setfor satisfying a condition that the voltage value thereof is less thanthat of the writing prevention voltage to be applied to the higher orderbit line 7b of the non-selected memory cell column wiring 18b whilebeing greater than or equal to that obtained by subtracting a thresholdvoltage V_(thn) of the NMOS transistor 15b from an N-side gate voltageV_(GN) to be applied to the NMOS transistor 15b in the non-selectedmemory cell column wiring 18b (i.e., greater than or equal to(V_(GN)−V_(thn))). Even with the aforementioned configuration, anon-volatile semiconductor memory device 31 can achieve advantageouseffects similar to those of the aforementioned exemplary embodiment.

Further, thus in the present invention, the source voltage is adjustablein addition to the gate voltage, and for instance, the selected bitvoltage V_(B2) of 4[V] can be applied to the higher order bit line 7a,while the non-selected source voltage V_(s1) of 4[V] can be applied tothe higher order source line 12b. Therefore, it is possible to reduce avoltage difference between the source and gate voltages to be applied tothe PMOS transistor 9c (in this case, source voltage of 4[V]−gatevoltage of 8[V]=voltage difference of 4[V]) and a voltage differencebetween the source and gate voltages to be applied to the NMOStransistor 15d (in this case, source voltage of 4[V]-gate voltage of0[V]=voltage difference of 4[V]). Accordingly, it is possible toremarkably relax electric fields applied to the gate insulating films ofthe PMOS transistor 9c and the NMOS transistor 15d, and to achieveenhancement in reliability of the transistors.

(2) Other Exemplary Embodiment

It should be noted that the present invention is not limited to theaforementioned exemplary embodiment, and a variety of modifications canbe made within the scope of the present invention. For example, anon-volatile semiconductor memory device may be applied that is obtainedby an arbitrary combination of the aforementioned non-volatilesemiconductor memory devices 1 and 25 according to the first exemplaryembodiment.

Further, the aforementioned exemplary embodiment has described the casethat a SONOS memory cell transistor capable of accumulating electriccharges into a silicon nitride film layer is applied as a memory celltransistor capable of accumulating electric charges into a chargeaccumulation layer. However, the present invention is not limited tothis, and any other various memory cell transistors may be applied, suchas a stack-type memory cell transistor in which a conductive polysiliconis disposed on a tunnel oxide film and electric charges are accumulatedinto the floating gate thereof.

Further, the aforementioned exemplary embodiment has described the caseof applying the non-volatile semiconductor memory device 1, 25 havingtotally four memory blocks 10a, 10b, 10c and 10d formed in the matrix oftwo rows and two columns. However, the present invention is not limitedto this. For example, a non-volatile semiconductor memory device may beapplied that has two memory blocks formed in two columns or in two rows.Alternatively, a non-volatile semiconductor memory device may be appliedthat has any other various number of memory blocks formed in a matrix oftwo rows and one column, a matrix of three rows and one column, a matrixof three rows and three columns or etc.

Further, the aforementioned exemplary embodiment has described the caseof applying the non-volatile semiconductor memory device 1 in which theplural memory cell transistors 103 are disposed between the bit line 4aand the source line 5a while one terminals thereof are connected to thebit line 4a and the other terminals thereof are connected to the sourceline 5a. However, the present invention is not limited to this. A NANDnon-volatile semiconductor memory device may be applied that a pluralityof memory cell transistors are disposed in series with respect to a bitline and the memory cell transistor in the bottom row is connected to asource.

Further, the exemplary embodiment of the present invention has explainedthat the device is formed on the P-type substrate. However, an N-typesubstrate may be used, or alternatively, an SOI substrate or etc. may beused. When any one of such substrates is used, the advantageous effectsof the present invention can be achieved even without formation of thedeep N-well DNW as long as the divided P-wells in the lower part of thememory cell region can be electrically separated.

The invention claimed is:
 1. A non-volatile semiconductor memory deviceincluding: a plurality of memory cell column wirings to which a chargeaccumulating voltage or a charge accumulating prevention voltage isapplied; and a plurality of memory cell transistors having an N-channeltype structure and disposed in a row and column matrix with respect tothe plurality of memory cell column wirings and a plurality of wordlines, the non-volatile semiconductor memory device causing a selectedmemory cell transistor in the plurality of memory cell transistors toaccumulate electric charges based on a voltage difference between thecharge accumulating voltage and a voltage to be applied to the wordlines, the non-volatile semiconductor memory device comprising: aplurality of first semiconductor switches formed by PMOS transistors,the first semiconductor switches being provided for the respectivememory cell column wirings; and a plurality of second semiconductorswitches formed by NMOS transistors, the second semiconductor switchesbeing provided for the respective memory cell column wirings, wherein,in a non-selected memory cell column wiring in which only non-selectedmemory cell transistors except for the selected memory transistor aredisposed, the first semiconductor switches are configured to be switchedon by means of a first gate voltage and to apply the charge accumulatingprevention voltage to the non-selected memory cell transistors whereas,in a selected memory cell column wiring in which the selected memorycell transistor is disposed, the second semiconductor switches areconfigured to be switched on by means of a second gate voltage and toapply the charge accumulating voltage to the selected memory celltransistor.
 2. The non-volatile semiconductor memory device according toclaim 1, further comprising: a first selection gate line equallyapplying the first gate voltage to the respective first semiconductorswitches; and a second selection gate line equally applying the secondgate voltage to the respective second semiconductor switches, whereinthe first semiconductor switches are configured to be switched on bymeans of a voltage difference between the charge accumulating preventionvoltage and the first gate voltage and to apply the charge accumulatingprevention voltage to the non-selected memory cell transistors, and thesecond semiconductor switches are configured to be switched on by meansof a voltage difference between the charge accumulating voltage and thesecond gate voltage and to apply the charge accumulating voltage to theselected memory cell transistor.
 3. The non-volatile semiconductormemory device according to claim 1, wherein each of the memory cellcolumn wirings is formed by a bit line and a source line, and each ofthe memory cell transistors is connected at one terminal thereof to thebit line and is connected at the other terminal thereof to the sourceline.
 4. The non-volatile semiconductor memory device according to claim3, wherein the bit line is formed by a higher order bit line and a lowerorder bit line connected to the higher order bit line through the firstsemiconductor switch, and each of the memory cell transistors isconnected at the one terminal thereof to the lower order bit line. 5.The non-volatile semiconductor memory device according to claim 3 or 4,wherein the source line is formed by a higher order source line and alower order source line connected to the higher order source linethrough the second semiconductor switch, and each of the memory celltransistors is connected to at the other terminal thereof to the lowerorder source line.
 6. The non-volatile semiconductor memory deviceaccording to claim 1, wherein either the first semiconductor switch orthe second semiconductor switch has a gate insulating layer disposedbetween a gate and a semiconductor substrate, the gate insulating filmhaving a film thickness of less than 13 [nm].
 7. The non-volatilesemiconductor memory device according to claim 1, wherein the memorycell transistors, the first semiconductor switches and the secondsemiconductor switches are formed on a unit well structure divided intoa predetermined number of wells.
 8. The non-volatile semiconductormemory device according to claim 1, wherein a memory array in which thememory cell transistors are aligned is formed on a plurality of P-wellsand the PMOS transistors are formed on an N-well electrically insulatingthe P-wells.
 9. The non-volatile semiconductor memory device accordingto claim 4, wherein either the first semiconductor switch or the secondsemiconductor switch has a gate insulating layer disposed between a gateand a semiconductor substrate, the gate insulating film having a filmthickness of less than 13[nm].